1. Field of the Invention
The present invention relates to the semiconductor device field and, more particularly, to a method for manufacturing a semiconductor device using an SOI (semiconductor on insulator) substrate.
2. Description of the Prior Art
In a method for manufacturing semiconductor devices, a substrate of monocrystalline silicon is provided with semiconductor elements by using a process of introducing a dopant of a Group III or Group Velement into the silicon substrate.
This ion implantation technique is known as a method for creating a diffusion region. Since this technique has advantages in adjusting dopant density and depth of diffusion, it is well used to the manufacture of semiconductor devices.
A method for manufacturing a semiconductor device, specifically a CMOS (complementary metal oxide semiconductor) type transistor, using an ion implantation technique is described herein.
A SIMOX (separation by implanted oxygen) substrate is prepared as shown in FIG. 1A which is a SOI (semiconductor on insulator) substrate. The SIMOX substrate has a structure where an oxide layer 4 is applied on a substrate 2 and a semiconductor layer 6 is applied on the oxide layer 4.
Referring to FIG. 1B, field oxide layers 8a, 8b and 8c are formed in the semiconductor layer 6 by a Local Oxidation of Silicon (LOCOS) technique to divide the silicon substrate into the plural insulated islands 10a and 10b, and gate oxidation layers 12a and 12b are formed on the island 10a and 10b by thermal oxidation.
To adjust the threshold voltage of a transistor to be manufactured to a predetermined value, a dosage of dopant needs to be injected into a channel region which is to be in the insulated islands. Assume that a NMOS (N-channel metal oxide semiconductor) type transistor and a PMOS (P-channel metal oxide semiconductor) type transistor which are of different kinds are provided on the silicon substrate. Then, ion implantation is implemented using two respective resist pattern masks. Referring to FIG. 1C, after a resist pattern 40 covers what is to be an PMOS type transistor, the substrate is subjected to an ion implantation step to create a channel region 20 of P- type with a predetermined threshold as shown in FIG. 2A. Removing the resist pattern 40, a resist pattern 42 covers what is to be a NMOS type transistor (FIG. 2A), and then the substrate is subjected to an ion implantation step to create a channel region 21 of P-type with a predetermined threshold voltage (see FIG. 2B). The resist pattern 42 then is removed.
Next, after a cleaning step, a conductive layer of polysilicon is applied on the entire surface of the substrate. After forming a resist pattern on the conductive layer, the conductive layer is etched by using a resist pattern (not shown) as a mask to form gate electrodes 16a and 16b. Then the resist pattern is removed (see FIG. 2C).
Next, ion implantation is implemented to create sources and drains. This ion implantation is applied to each of the NMOS type transistor and the PMOS type transistor using two respective masks. Specifically, referring to FIG. 3A a resist pattern 44 is applied to what is to be the PMOS type transistor, and then the substrate is subjected to an ion implantation step to create an N+ source 22 and an N+ drain 22. Furthermore, referring to FIG. 3B, after removing the resist pattern 44, a resist pattern 46 is applied to what is to be the NMOS type transistor, and then the substrate is subjected to an ion implantation step to create a P+ source 23 and a P+ drain 23. Then the resist pattern 46 is removed (see FIG. 3C).
However, a method for manufacturing a semiconductor device using two such ion implantation steps has the following problems.
As is described above, the two ion implantation steps are not able to be performed truly successively. A step of forming the gate electrodes 16a and 16b must be implemented between the two ion implantation steps. That is, the two ion implantation steps cannot be performed with a single resist pattern. Therefore, the operations are complicated because the resist pattern must be replaced.
Also, a device for ion implantation is different from that for forming the gate electrode. Therefore, the operations are complicated because the silicon substrate is moved from one device to another.